The present invention generally relates to an emitter coupled logic circuit, and in particular to an emitter coupled logic circuit capable of driving a load capacitor having a large capacitance.
An emitter coupled logic circuit (hereafter simply referred to as an ECL circuit) is used in order to speed up the operation of a logic circuit. A transistor of the ECL circuit is not driven up to a saturated state, and is switched between an active state and a cut-off state. In the case where the ECL circuit drives a load capacitance having a large capacitance, the operation of the ECL circuit is delayed. Therefore, it is desirable to speed up the operation of the ECL circuit.
It is well known that a load capacitance coupled with an output terminal of the ECL circuit increases as the integration density of a semiconductor integrated circuit which implements the ECL circuit increases. This is because a wiring pattern formed on a semiconductor chip is apt to be lengthened as the integration density increases. When a potential of the output terminal of the ECL circuit is switched from a high-level (hereafter simply referred to as "H") to a low-level (hereafter simply referred to as "L"), a charge stored in the load capacitance is discharged by a load impedance which is coupled with the output terminal. Therefore as the load impedance is reduced, a time necessary for the potential at the output terminal to completely reach "L" can be reduced. Such a time is referred to as a fall time.
However, as the load impedance decreases, the power consumed in the ECL circuit increases. It is to be noted that the load impedance cannot be allowed to exceed a predetermined balue because there is a limit with respect to the total power consumption in the integrated circuit. For this reason, the time necessary for the potential at the output terminal of the ECL circuit to be switched to "L" (the fall time) cannot be effectively shortened.
Another ECL circuit has been proposed in the U.S. Pat. No. 4,539,493. This proposed ECL circuit employs an emitter follower circuit and utilizes a fact that when the output of the ECL circuit is switched from "H" to "L", a reverse logic output is switched from "L" to "H". The level change of the reverse logic output is supplied to a base of the emitter follower transistor through a capacitive coupling. Thereby the base level of the emitter follower transistor is increased, so that the change from "H" to "L" can be made faster. However, the operating speed of the proposed ECL circuit still depends on the magnitude of the load capacitance. A similar ECL circuit is disclosed in the U.S. Pat. No. 4,276,485, and has a similar disadvantage.